The present invention relates to a semiconductor memory device, and more particularly to a dynamic type semiconductor memory device employing so-called shared sense amplifier scheme.
Semiconductor memory devices have come to have large memory capacities such as 256K bits, 1 Mega bits, and the internal signals read-out from memory cells are reduced to a minute level. In such memory devices, those employing one-transistor type memory cells having one transistor and one capacitor are generally utilized. In accompanied by the increase in the memory capacity, the number of memory cells coupled to the respective bit line has become large and effective capacitance of the respective bit line has also become large. This increase in the bit line capacitance lowers a potential change at the bit line by the read-out signal from a memory cell.
Under such circumstance, the so-called shared sense amplifier scheme has been proposed. According to the shared sense amplifier scheme, the respective pair of bit lines are splitted into two pairs of first and second bit line segments and one pair of the bit line segments are electrically connected to a sense amplifier. The details of the shared sense amplifier scheme is disclosed in the U.S. Pat. No. 4,366,559 issued to Misaizu et al. In the shared sense amplifier scheme, it has been practised to arrange a plurality pairs of first bit line segments in parallel at one side of sense amplifiers arranged in line and a plurality pairs of second bit line segments in parallel at the other side of the sense amplifiers. Accordingly, in the shared sense amplifier, the capacitance of the respective bit line segment is reduced to half as compared to the conventional scheme, and it is possible to perform more stable and reliable sensing operation.
The conventional semiconductor memory device suffers, however, from the problem concerning the noise generated by coupling capacitance (C.sub.BB) between the bit lines arranged in parallel. Considering this problem in regard to the so-called folded bit line arrangement, a pair of bit lines which are connected to the same sense amplifier are always in anti-phase relation to each other when activated and therefore act so as to reduce the differential potential between the true and complementary bit lines constituting the bit line pair. When bit line pairs which are adjacent to the certain bit line pair concerned act in anti-phase relation to the certain bit line pair also, the coupling capacitance C.sub.BB between the certain bit line pair and the adjacent bit line pairs acts so as to reduce the differential potential between the bit lines of the certain bit line pair.
In other words, the coupling capacitance C.sub.BB between the bit lines substantially causes lowering in the sensitivity of the sense amplifier. As the integration density and the memory capacity are increased and the spacing between the wirings is consequently reduced, that is, as the spacing between the bit lines is reduced, the coupling capacitance C.sub.BB increases and becomes a critical problem.
Thus, the memory device employing the folded bit line scheme is readily affected by the noise generated by the coupling capacitance between the bit lines.